A master or initiator is an agent that initiates transactions on the PCI bus. The master controls data transfer to and from the target. To initiate a data transfer, the master must assert the required signals, and keep them asserted until they are acknowledged. A target or slave is an agent that responds to a transaction initiated on the PCI bus (by a master agent) and intended for it. To indicate completion of a transaction, a target must provide an acknowledge cycle, which can include error or retry signals. The PCI interface automatically inserts any wait states needed to prevent the master from timing out, allowing high-speed PCI transactions to be processed by relatively slow back-end devices.
A PCI back-end device is defined as any device that stores, sends, or retrieves information using the PCI bus (for example: video cards, memory cards, disk drives, and multimedia cards). In a conventional configuration, the back-end device is considered a target. The target interface logic and memory can either is encapsulated in a controller device or fully or partially integrated into the back-end device.
The back-end device is physically remote from the processor local bus. Back-end devices communicate with the host processor across a PCI bridge, which serves as a layer of device management between back-end devices and the host, thereby streamlining data transfer. The interface supports bus mastering, which allows intelligent devices to access main memory directly.
In order to understand the operation of the PCI module that was tested, it is necessary to present and explain each of the signals that will be used on this device. As specified in the PCI Bus Specification, many of these signals are active low, which means that it is asserted at low voltage. We will distinguish this type of signal from the others using an 'n' in front of any signal that is active low. These definitions are taken from the PCI Local Bus Specifications (2.2), as the expected behavior of the signals on a PCI device.
The signals used by this device can be divided into different groups. These types are the following:
in - Input is a standard input-only signal.
out - Totem Pole Output is a standard active driver.
t/s - Tri-State is a bi-directional, tri-state input/output pin.
s/t/s - Sustained Tri-State is an active low tri-state signal owned and driven by one and only one agent at a time.
PCI pin functions can vary depending on the purpose of the device. In other words the behavior of a pin in a PCI device that is a target is not necessary the same as if it were a master. Since our interest is only on a PCI device that will perform as a target, we will only present the functions of the pins in a target. The block diagram below shows the signals used on a target PCI device.
Block diagram of a PCI device showing Required and Optional Signals.
The PCI pin definitions will be organized by functional group. The first of the functional are the System Pins; these are signals that come from the system in which the device in mounted. Most of the time a processor regulates these signals.
System pins on the PCI Target device.
Name | Type | Behavior | Description |
CLK | in | in | Clock provides timing for all transactions on PCI and is an input to everyPCI device. All other PCI signals, except nRST, are sampled on the rising edge of CLK and all other timing parameters are defined with respect to this edge. PCI operates up to 33 MHz. |
nRST | in | in | Reset is used to bring PCI-specific registers, sequencers, and signals to a consistent state. Anytime nRST is asserted all PCI output signals must be driven to their benign state. In general, this means they must be asynchronously tri-stated. nRST may be asynchronous to CLK when asserted or deasserted. Although asynchronous, deassertion is guaranteed to be a clean, bounce-free edge. Except for configuration accesses, only devices that are required to boot the system will respond after reset. |
The second functional group is the Address and Data Pins. The signals on these pins are the ones that carry the commands and address of the data that should be transferred through the device.
Address and Data pins on the PCI Target device.
Name | Type | Behavior | Description |
AD[31::0] | t/s | Bi-dir. | Address and Data are multiplexed on the same PCI pins. A bus transaction consists of an address 3 phase followed by one or more data phases. PCI supports both read and write bursts. The address phase is the clock cycle in which nFRAME is asserted. During the address phase AD[31::00] contain a physical address (32 bits). For I/O, this is a byte address; for configuration and memory, it is a DWORD address. During data phases AD[07::00] contain the least significant byte(lsb) and AD[31::24] contain the most significant byte (msb). Write data is stable and valid when nIRDY is asserted and read data is stable and valid when nTRDY is asserted. Data is transferred during those clocks where both nIRDY and nTRDY are asserted. |
nC/BE[3::0] | t/s | in | Bus Command and Byte Enables are multiplexed on the same PCI pins. During the address phase of a transaction, nC/BE[3::0] define the bus command. During the data phase nC/BE[3::0] are used as Byte Enables. The Byte Enables are valid for the entire data phase and determine which byte lanes carry meaningful data. nC/BE[0] applies to byte 0 (lsb) and nC/BE[3] applies to byte 3 (msb). |
The Interface Control Pins are the signals that come from the PCI Bus and determine if the transaction start, stop, or end in combination with each other and with other signals.
Interface Control pins on the PCI Target device.
Name | Type | Behavior | Description |
nFRAME | s/t/s | in. | Cycle Frame is driven by the current master to indicate the beginning and duration of an access. nFRAME is asserted to indicate a bus transaction is beginning. While nFRAME is asserted, data transfers continue. When nFRAME is deasserted, the transaction is in the final data phase or has completed. |
nIRDY | s/t/s | in. | Initiator Ready indicates the initiating agent's ability to complete the current data phase of the transaction. IRDY# is used in conjunction with TRDY#. A data phase is completed on any clock both IRDY# and TRDY# are sampled asserted. During a write, IRDY# indicates that valid data is present on AD[31::00]. Wait cycles are inserted until both IRDY# and TRDY# are asserted together. |
nTRDY | s/t/s | Bi-dir. | Target Ready indicates the target agent's ability to complete the current data phase of the transaction. nTRDY is used in conjunction with nIRDY. A data phase is completed on any clock both nTRDY and nIRDY are sampled asserted. During a read, nTRDY indicates that valid data is present on AD[31::00]. During a write, it indicates the target is prepared to accept data. Wait cycles are inserted until both nIRDY and nTRDY are asserted together. |
nSTOP | s/t/s | Bi-dir | Stop indicates the current target is requesting the master to stop the current transaction. |
nDEVESEL | s/t/s | Bi-dir | Device Select, when actively driven, indicates the driving device has decoded its address as the target of the current access. As an input, nDEVSEL indicates whether any device on the bus has been selected. |
IDSEL | in | in | Initialization Device Select is used as a chip select during configuration read and writes transactions. |
Bus Commands
Bus commands indicate to the target the type of transaction the master is requesting. Bus commands are encoded on the nC/BE[3::0] lines during the address phase.
Commands for the PCI device
nC_BE[3::0] | Command Type |
0000 | Interrupt acknowledge |
0001 | Special cycle |
0010 | I/O read |
0011 | I/O write |
0100 | Reserved |
0101 | Reserved |
0110 | Memory read |
0111 | Memory write |
1000 | Reserved |
1001 | Reserved |
1010 | Configuration read |
1011 | Configuration write |
1100 | Memory read multiple |
1101 | Dual address cycle |
1110 | Memory read line |
1111 | Memory write and invalidate |
PCI Characteristics
The PCI bus has 4 main characteristics:
- Synchronous
- Transaction/Burst oriented
- Bus mastering
- Plug-and-play
PCI is Synchronous
The PCI bus uses one clock. The clock runs at 33MHz by default but can run at higher rates if your hardware supports it.
The PCI bus is transaction oriented.
1. A transaction is started
2. A starting address is specified (one clock cycle)
3. One or many data cycles follow
4. The transaction is ended.
Once the address is specified, many data cycles can follow without the need to retransmit address information. The address is auto-incremented at each data cycle. To specify a different address, the transaction would have to be stopped, and a new one started. For this reason, PCI bandwidth is best utilized in burst mode.
PCI Bus Mastering
PCI transactions work in a master-slave relationship. A master is an agent that initiates a transaction (can be a read or a write).
While the host CPU is often the bus master, all PCI boards can potentially claim the bus and become a bus master.
While the host CPU is often the bus master, all PCI boards can potentially claim the bus and become a bus master.
PCI is PnP (Plug-and-Play)
The last feature is an important part of plug-and-play. Each board responds to some addresses, but the addresses to which it responds can be programmed (i.e. each board generates its own board/chip-select signal(s)). This allows the OS to "map" the address space of each board appropriately.
PCI Memory Spaces
PCI defines 3 memory spaces where you can read and write data.
When a transaction starts, the master specifies the starting address of the transaction, if it's a read or a write, AND which space he wants to speak to.
1. Memory space
2. IO space
3. Configuration space
They work as follow:
- The memory and IO spaces are the workhorse spaces. They are "relocatable" (i.e. the addresses at which each board responds can be moved).
- The configuration space is used for PnP. It's a space where each board has to implement very specific registers at very specific addresses, so that the host-CPU/OS can figure out what is each board's identity/abilities/requirements. The host CPU/OS can also write to enable and configureboards other two spaces.
- This space is fixed and always starts at address 0 for all PCI boards; so one line of the PCI connector is used as board-select (for this space only).
To be compliant, a PCI board needs to implement configuration space. Memory and IO spaces are optional, but one or both are always used in practice.
PCI Voltage
PCI boards currently use 3.3V or 5V signaling. The connectors and correspondingly the boards, are "keyed" to identify whether it is 3.3V or 5V compliant. This is to ensure that a 3.3V only board cannot be plugged into a 5V-only bus.
PCI Prototype Card
Here is a snapshot of the work-in-progress Target PCI Card with a brief description of the populated components:
Xilinx Spartan II FPGA (XC2S100) TQFP144
XC1801SO20 Configuration PROM
FTDI FT245M USB Interface Chip
TPS7225 2.5V Fixed Voltage Regulator (Xilinx Core Voltage Supply)
5V 32-Bit PCI Card Interface
The Xilinx Spartan II was selected based on several factors. First, Xilinx offers a free downloadable Webpack for this family, and the JTAG programmer is straight forward to construct. This allows me to spend little time (and money) to setup and get started with the tools. Also, the Webpack is not time limited, or constrained in any way that would prevent me from taking advantage of all the features available on the FPGA. Secondly, although the available core voltages for this device are 1.8V and 2.5V, it still maintains 5V PCI-Bus compatibility on the I/O ring. This is important since most of the test PCs I'm willing to risk during the prototyping stage all operate on a 5V PCI Bus.
I have also added a USB interface chip to this card for future debugging operations or to integrate external add-on devices.
Currently the card is capable of responding to I/O and Memory space reads and writes. The initial tests used a fixed address to generate hits in both the I/O and Memory areas. I have just completed the implementation of the configuration space write operation (specific registers only) to allow for OS PnP (plug and play). This will allow the OS to give the PCI Target Card a valid I/O and Memory space address automatically.
Here is a screenshot of the configuration simulation performed in ALDEC Active-HDL. This screenshot shows two PnP addresses being written to the internal PCI Target Card registers ba0 and ba1 respectively.
Description of Events
PC asserted the nFRAME signal on rce (rising clock edge) 1 indicating the start of a transaction. At the same time, it places the configuration address of 10h (Base Address 0) on the AD lines and sets nCBE to 1011 (Configuration Write). Also, the IDSEL line is asserted indicating that this specific device has been selected. The IDSEL line is unique to each PCI bus slot, and is used at start-up to configure each card with appropriate addresses.
By rce 2, the PC has asserted the nIRDY, indicating that the data is ready to be written (200h). The PCI Target card asserts the nDEVSEL indicating that it has acknowledged the fact that it has been selected. This is also the time when the base address register 0 (ba0) records the PnP address.
Since by rce 3 the nTRDY signal has not yet been asserted, the PC will continue to hold the nIRDY signal low.
By rce 4, the transaction has completed, and the bus returns to the idle state.
This operation is repeated again to write the second PnP base address to ba1.
October 3rd, 2004
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